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THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 1 / 17 thine electronics, inc. security e thc 63lvdm83 d 24 b it color lvds transmitter general description the thc63lvdm83 d transmitter is designed to sup port pixel data transmission between host and flat panel display up to 1080p/wuxga resolutions. the thc63lvdm83 d co nverts 28bits of lv cmos data into four openldi( lvds ) data stream s . the transmitter can be programmed for rising edge or falling edge clock through a dedicated pin. at a transmit clock frequency of 160mhz, 24bits of rgb data and 4bits of timing and control data (hs ync, vsync, de, cont1) are transmitted at an effective rate of 1120mbps per openldi( lvds ) channel. application ? medium and s mall s ize p anel ? tablet pc / notebook pc ? security camera / industrial camera ? multi function printer ? industrial e quipment ? medical e quipm ent m onitor features ? compatible with tia/eia - 644 lvds standard ? 7:1 openldi( lvds ) transmitter ? operating temperature range : 0 to +70 ? c ? no special start - u p sequence required ? spread spectrum clocking t olerant up to 100khz f requency m odulation and +/ - 2. 5% d eviations. ? wide d ot c lock r ange: 8 to 160mhz s uited for tv signal : ntsc(12.27mhz) - 1080p(148.5mhz) pc signal : qvga(8mhz) - wuxga(154mhz) ? 56 pin tssop package ? 1.2v to 3.3v lv cmos / inputs are s upported. ? lvds swing is reducible as 200m v by rs - pin to reduce emi and power consumption. ? pll requires no external components. ? power d own m ode. ? input clock triggering edge is selectable by r/f - pin ? e u rohs compliant. block diagram figure 1 . block diagram 7 pll ta +/ - tb +/ - tc +/ - td +/ - tclk +/ - r/f /pdwn ta0 - 6 tc0 - 6 td0 - 6 transmitter (8 to 160mhz) cmos/ttl 7 rs 7 tb0 - 6 7 inputs clock (lvds) 8 - 160mhz data (lvds) (56 - 1120mbit/on each lvds channel) clkin thc63lvdm83 d cmos/ttl parallel to serial 7 pll ta +/ - tb +/ - tc +/ - td +/ - tclk +/ - r/f /pdwn ta0 - 6 tc0 - 6 td0 - 6 transmitter (8 to 160mhz) cmos/ttl 7 rs 7 tb0 - 6 7 inputs clock (lvds) 8 - 160mhz data (lvds) (56 - 1120mbit/on each lvds channel) clkin thc63lvdm83 d cmos/ttl parallel to serial
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 2 / 17 thine electronics, inc. security e pin diagram figure 2 . pin diagram
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 3 / 17 thine electronics, inc. security e pin description pin name pin # direction type description ta+, ta - 47, 48 output lvds lvds data out tb+, tb - 45, 46 tc+, tc - 41, 42 td+, td - 37, 38 tclk+, tclk - 39, 40 lvds clock out ta0 ~ ta6 51, 52, 54, 55, 56, 3, 4 input lvcmos pixel data input tb0 ~ tb6 6, 7, 11, 12, 14, 15, 19 tc0 ~ tc6 20, 22, 23, 24, 27, 28, 30 td0 ~ td6 50, 2, 8, 10, 16, 18, 25 /pdwn 32 h : normal o peration l : power d own ( a ll outputs are hi - z) rs 1 lvds s wing m ode, vref s elect see fig . 7 , 8 vref : is input reference voltage r/f 17 input clock triggering edge select h : rising e dge l : falling e dge clkin 31 input clock vcc 9, 26 power - power supply pin s for lv cmos input s and digital circuit. gnd 5, 13, 21, 29, 53 ground pins for lv cmos i nputs and d igital c ircuitry . lvds vcc 44 power supply pins for lvds outputs. lvds gnd 36, 43 49 ground pins for lvds outputs. pll vcc 34 power supply pin for pll c ircuitry. pll gnd 33, 35 ground supply pin for pll c ircuitry . table 1 . pin description rs pin lvds swing small swing input support vcc 350mv n/a 0.6 to 1.4v 350mv rs=vref gnd 200mv n.a
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 4 / 17 thine electronics, inc. security e absolute maximum ratings parameter min max unit all supply voltage (vcc , lvds vcc, pll vcc ) - 0.3 +4.0 v lvcmos input voltage - 0.3 vcc + 0.3 v lvds output pin - 0.3 vcc + 0.3 v output current - 30 30 ma junction temperature - +125 ? c storage temperature - 55 +150 ? c reflow peak temperature - +260 ? c reflow peak temperature time - 10 sec maximum power d issipation @+25 ? c - 1.8 w table 2 . absolute maximum rating s recommended operating conditions symbol parameter min typ max uni t vcc, lvds vcc pll vcc all supply voltage 3.0 3.3 3.6 v ta operating ambient temperature 0 25 +70 ? c - clock frequency 8 - 160 mhz table 3 . recommended operating conditions absolute m aximum r atings are those value s beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of e lectrical characteristics table4, 5, 6, 7 specify conditions for device operation. absolute m aximum r ating value also include s behavior of overshooting and undershooting. equivalent lvds output schematic diagram figure 3 . lvds output schematic diagram lvds_outp lvds_outn in_n in_p 3.5ma
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 5 / 17 thine electronics, inc. security e power consumption over recommended operating supply and temperature range unless otherwise specified symbol parameter condition s typ * max unit i tccw lvds transmitter operating current worst case pattern (fig.4) rl=100 ? , cl=5pf, f=85mhz, rs=vcc 61 67 ma rl=100 ? , cl=5pf, f=135mhz, rs=vcc 77 83 ma rl=100 ? , cl=5pf, f=160mhz, rs=vcc 84 92 ma rl=100 ? , cl=5pf, f=85mhz, rs=gnd 50 56 ma rl=100 ? , cl=5pf, f=135mhz, rs=gnd 65 71 ma r l=100 ? , cl=5pf, f=160mhz, rs=gnd 73 80 ma i tccs lvds transmitter power down current /pdwn=l, all inputs=l or h - 10 a *typ values are at the conditions of vcc=3.3v and t a = +25 o c table 4 . power consumption worst case pattern x=a,b,c,d figure 4 . worst case pattern clkin tx0-6
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 6 / 17 thine electronics, inc. security e electrical characteristics lvcmos dc specifications over recommended operating supply and temperature range unless otherwise specifi ed symbol parameter conditions min typ * max unit v ih high level input voltage rs= vcc or gnd 2.0 - vcc v v il low level input voltage rs= vcc or gnd gnd - 0.8 v v ddq 1 small swing voltage 1.2 - 2.8 v v ref input reference voltage small swing (rs=v ddq /2) - v ddq /2 - v sh 2 small swing high level input voltage v ref= v ddq /2 v ddq /2 +100m v - - v v sl 2 small swing low level input voltage v ref= v ddq /2 - - v ddq /2 - 100mv v i inc input current gnd ? v in ? vcc - - ? 10 ? a *typ values are at the conditions of vcc=3.3v a nd t a = +25 o c notes : 1 v ddq voltage defines the max voltage of small swing input s at rs=vref . it is not an actual input voltage. 2 small swing signal s are applied to ta0 - 6, tb0 - 6, tc0 - 6, td0 - 6 and clkin. table 5 . lv - cmos dc s pecifications lvds transmitter dc specifications over recommended operating supply and temperature range unless otherwise specified symbol parameter conditions min typ * max unit vod differential output voltage rl=100 normal swing rs= vcc 250 350 450 mv reduced swing rs= gnd 1 00 200 300 mv ? vod change in vod between complementary output states rl=100 - - 35 mv voc common mode voltage 1.125 1.25 1.375 v ? voc change in voc between complementary output states - - 35 mv i os output short circuit current v out = gnd , rl=100 - - - 24 ma i oz output tri - state current /pdwn= gnd , v out = gnd to vcc - - ? 10 ? a *typ values are at the conditions of vcc=3.3v and t a = +25 o c table 6 . lvds transmitter dc specifica tion s
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 7 / 17 thine electronics, inc. security e lvcmos & lvds transmitter a c specifications over recommended operating supply and temperature range unless otherwise specified symbol parameter min typ max unit t tcit clk in transition time - - 5.0 n s t tcp clk in period 6.25 t 125 ns t t ch clk in high time 0.35t 0.5t 0.65t ns t tcl clk in low time 0.35t 0.5t 0.65t ns t tcd clk in to tclk+/ - delay - 3t - ns t ts lvcmos data setup to clk in 2.0 - - ns t th lvcmos data hold from clk in 0.0 - - ns t lvt lvds transition time - 0.6 1.5 ns t top 1 output data position0 (t= 6.25 ns ~ 20ns) - 0.15 0.0 +0.15 ns t top0 output data position1 (t= 6.25 ns ~ 20ns) t/7 - 0.15 t/7 t/7+0.15 ns t top6 output data position2 (t= 6.25 ns ~ 20ns) 2t/7 - 0.15 2t/7 2t/7+0.15 ns t top5 output data position3 (t= 6.25 ns ~ 20ns) 3 t/7 - 0.15 3t/7 3t/7+0.15 ns t top4 output data position4 (t= 6.25 ns ~ 20ns) 4t/7 - 0.15 4t/7 4t/7+0.15 ns t top3 output data position5 (t= 6.25 ns ~ 20ns) 5t/7 - 0.15 5t/7 5t/7+0.15 ns t top2 output data position6 (t= 6.25 ns ~ 20ns) 6t/7 - 0.15 6t/7 6t/7+0.15 ns t tp ll phase lock loop set - - 10.0 ms *typ values are at the conditions of vcc=3.3v and t a = +25 o c table 7 . lvcmos & lvds transmitter ac specifications lv cmos input figure 5 . clkin transmission time lvds output lvds output load figure 6 . lvds output load and transmission time clk in 90% 10% 90% 10% t tcit t tcit v o c v o d 5 0 5 0 5 p f t n + t n - 0 % 2 0 % 8 0 % 1 0 0 % 0 v t l v t t l v t v o d ( h ) v o d ( l )
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 8 / 17 thine electronics, inc. security e ac timing diagrams lvcmos inputs normal swing input note : clkin : soli d li ne denotes the setting of r/f=gnd dashed line denotes the setting of r /f = vcc figure 7 . lvcoms inputs and lvds clock output timing 1 small swing inputs note : clkin : solid line denotes the setting of r/f=gnd dashed line denotes the setting of r/f = vcc figure 8 . lvcmos inputs and lvds output timing 2 rs vod vcc 0.6 ~ 1.4v gnd 200mv 350mv rs vref vcc --- 0.6 ~ 1.4v v ddq /2 gnd --- t t c p t t s t t h t t c h t t c l c l k i n t x 0 - t x 6 t t c d t c l k + t c l k - v c c g n d g n d v c c v o c v c c / 2 v c c / 2 v c c / 2 v c c / 2 v c c / 2 t t c p t t s t t h t t c h t t c l c l k i n t x 0 - t x 6 t t c d t c l k + t c l k - v d d q g n d g n d v d d q v r e f v o c v r e f v d d q / 2 v d d q / 2 v d d q / 2 v d d q / 2 v d d q / 2
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 9 / 17 thine electronics, inc. security e lvds output data position figure 9 . lvds output data position phase lock loop set time figure 1 0 . pll lock loop set time v diff = 0v v diff = 0v tclk+/- t t op1 t top0 t top6 t top5 t top4 t top3 t top2 td6 td5 td4 td3 td2 td1 td0 td+/- tc6 tc5 tc4 tc3 tc2 tc1 tc0 tc+/- tb6 tb5 tb4 tb3 tb2 tb1 tb0 tb+/- ta6 ta5 ta4 ta3 ta2 ta1 ta0 ta+/- (differential) next cycle previous cycle 2.0v clkin /pdwn tclk+/- 3.0v vcc t tpll v diff = 0v
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 10 / 17 thine electronics, inc. security e s pread spectrum clocking t olerant figure 1 1 . spread spectrum clocking t olerant the graph indicate s the range that the ic works normally under ss c lock inpu t operation. the results are measured with a typical sample on condition of +25 c o and 3.3v , therefore the se value s are for reference and do not guarantee the performance of a product under other circumstance . lvds data timing diagram figure 12 . lvds data timing diagram v d i f f = 0 v v d i f f = 0 v t c l k + / - ( d i f f e r n t i a l ) t x + / - x = a , b , c , d p r e v i o u s p i x e l d a t a p i x e l d a t a t x 6 t x 5 t x 4 t x 3 t x 2 t x 1 t x 0
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 11 / 17 thine electronics, inc. security e for display application THC63LVDM83D pixel data mapping for jei d a format (6bit, 8 b it application) note : use ta to tc channels and op en td channel for 6bit application . table 8 . data mapping for jeida format 6 b it 8 b it ta0 r2 r2 ta1 r3 r3 ta2 r4 r4 ta3 r5 r5 ta4 r6 r6 ta5 r7 r7 ta6 g2 g2 tb0 g3 g3 tb1 g4 g4 tb2 g5 g5 tb3 g6 g6 tb4 g7 g7 tb5 b2 b2 tb6 b3 b3 tc0 b4 b4 tc1 b5 b5 tc2 b6 b6 tc3 b7 b7 tc4 hsync hsync tc5 vsync vsync tc6 de de td0 - r0 td1 - r1 td2 - g0 td3 - g1 td4 - b0 td5 - b1 td6 - n/a
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 12 / 17 thine electronics, inc. security e THC63LVDM83D pixel data mapping for vesa format (6bit, 8 b it application) note : use ta to tc channels and open td channel for 6bit application . table 9 . data mapping for vesa format 6 b it 8 b it ta0 r0 r0 ta1 r1 r1 ta2 r2 r2 ta3 r3 r3 ta4 r4 r4 ta5 r5 r5 ta6 g0 g0 tb0 g1 g1 tb1 g2 g2 tb2 g3 g3 tb3 g4 g4 tb4 g5 g5 tb5 b0 b0 tb6 b1 b1 tc0 b2 b2 tc1 b3 b3 tc2 b4 b4 tc3 b5 b5 tc4 hsync hsync tc5 vsync vsync tc6 de de td0 - r6 td1 - r7 td2 - g6 td3 - g7 td4 - b6 td5 - b7 td6 - n/a
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 13 / 17 thine electronics, inc. security e typical connecti on figure 1 3 . typical connecti on diagram
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 14 / 17 thine electronics, inc. security e note s 1) cable connection and disconnection do n o t connect and disconnect the lvds cable, when the power is supplied to the system. 2) gnd connection connect each gnd of the pcb which thc63lvdm83 d and lvds - rx on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3) multi drop connection multi drop connection is not recommended. figure 14 . multi drop connection 4) asynchronous use asynchronous using such as following systems is not recommended. figure 15 . asynchronous u se lvds - rx thc 63lvdm83d lvds - rx tclk + tclk - ic clkout clkout data data lvds - rx lvds - rx ic tclk + tclk - tclk + tclk - clkout data data thc 63lvdm83d thc 63lvdm83d ic tclk + tclk - tclk + tclk - clkout clkout data data ic thc 63lvdm83d thc 63lvdm83d
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 15 / 17 thine electronics, inc. security e package figure 16 . package d iagram 1 . 0 0 r e f 0 . 6 0 + / - 0 . 1 5 0 . 2 5 g a u g e p l a n e 0 . 5 0 . 1 7 ~ 0 . 2 7 1 4 . 0 0 + / - 0 . 1 0 s 0 . 1 0 s 6 . 1 0 + / - 0 . 1 8 . 1 0 n o m 0 . 0 5 ~ 0 . 1 5 1 . 2 0 m a x s e a t i n g p l a n e u n i t : m m
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 16 / 17 thine electronics, inc. security e reference land pattern figure 17 . reference of land pattern the reco mmendation mount ing method of thine device is reflow soldering. t he reference pattern is using the calculation result on condition of reflow soldering. notes this land pattern design is a calculated value based on jeita et - 7501. p lease take into consideration in an actual substrate design about enough the ease of mounting, the intensity of connection, the density of mounting, and the solder paste used, etc the optimal land pattern size changes with these parameters. please use the value shown by the land pattern as reference data. cy1= h e = e= e= ttyp.= gmin= b= zmax= xmax= zmax/2 5 . 5 0 9 . 3 0 0.60 8.100 6.10 10.34 0.500 1 . 9 0 0.200 0 . 4 7 0 unit mm package land pattern
THC63LVDM83D_rev.4. 3 0_e copyright ? 201 7 thine electronics , inc. 17 / 17 thine electronics, inc. security e notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which m ay not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know - how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applicat ions: audio - video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. this product must not be used for applications that require extremely high - reliability/safety such as a erospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unle ss the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified product") in this data sheet. thine electronics, inc. (thine) accepts no liability whatsoever for any product other than the specified pr oduct for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi - conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation - proof. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product. except where mandated by applicable law or deemed necessary by thine based on the users reque st, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. the damages may cause a smoking and ignition. therefor e, you are enc ouraged to implement safety measures by adding protection devices, such as fuses. thine electronics, inc. sales@thine.co.jp

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